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[ARM-PowerPC-ColdFire-MIPS] FIFO_Buffer

Description: 同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序，erilog编写~具有较强的参考价值~ -Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~
Platform: | Size: 69632 | Author: 张勇奇 | Hits:

[OS Develop] dfifo

Description: verilog，异步一进一出的例子，空满的标志。-verilog, into an asynchronous one example, air-filled logo.
Platform: | Size: 2048 | Author: 陈虎 | Hits:

[Windows Develop] sdh

Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
Platform: | Size: 6144 | Author: 韩冰 | Hits:

[source in ebook] yibu_FIFO_design

Description: 异步FIFO实例，精通verilog hdl中的例子，供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning
Platform: | Size: 2048 | Author: 林 | Hits:

[VHDL-FPGA-Verilog] asy_FIFO

Description: 用Verilog实现FIFO的异步设计，里面有详细的代码和各个模块的代码，经过调试可以使用-asynchronous FIFO design
Platform: | Size: 3072 | Author: fifo.v | Hits:

[OS Develop] SC16C752B

Description: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics.
Platform: | Size: 160768 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] sdfsdFifo

Description: 这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out
Platform: | Size: 1024 | Author: Yongjie | Hits:

[OS program] aFIFO

Description: 实现了一个异步fifo功能的verilog模块-An asynchronous fifo function verilog module
Platform: | Size: 2048 | Author: 董萱 | Hits:

[Windows Develop] VFIFOzipe

Description: 用verilog实现异步FIFO，代码中有两个模块，使用时时注意顶层模块和底层模块，用quartus2即可打开直接使用。 -Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
Platform: | Size: 2048 | Author: zcl1233 | Hits:

[Windows Develop] aasyn_fiffos

Description: verilog编写的异步fifo源代码，asyn_fiifo.v为顶层，调用其他四个文件， -verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
Platform: | Size: 2048 | Author: mmzz3211 | Hits:

[VHDL-FPGA-Verilog] LL

Description: verilog语言描述的异步FIFO设计。-verilog language to describe the asynchronous FIFO design.
Platform: | Size: 6144 | Author: whh | Hits:

[VHDL-FPGA-Verilog] FIFO_V1

Description: 同步FIFO和异步FIFO程序，希望对大家有用！verilog程序。-Synchronous FIFO and asynchronous FIFO procedures, and hope to be useful! The verilog procedure.
Platform: | Size: 5120 | Author: dean | Hits:

[VHDL-FPGA-Verilog] FIFOverilog

Description: 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
Platform: | Size: 11264 | Author: 章鱼 | Hits:

[VHDL-FPGA-Verilog] sync-and-asyn_FIFO_verilog

Description: 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
Platform: | Size: 1715200 | Author: gt | Hits:

[VHDL-FPGA-Verilog] async_pulse

Description: asynchronous fifo with pulse input write by verilog code
Platform: | Size: 2048 | Author: Long | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 利用verilog写的异步FIFO的一种写法-Using a written verilog write asynchronous FIFO
Platform: | Size: 1024 | Author: 丁海军 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 深度256的异步fifo 使用verilog语言编写的，能够实现简单的读写，存储功能！-256 the depth of asynchronous FIFO
Platform: | Size: 1024 | Author: 王先生 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用Verilog实现异步fifo的功能-Use Verilog implementation of asynchronous fifo functionality
Platform: | Size: 1205248 | Author: Amy_nmw | Hits:

[VHDL-FPGA-Verilog] asyn_fifo

Description: 该源码包是异步fifo的Verilog语言模型，主要包括2个部分：异步fifo控制模块、测试文件。(The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.)
Platform: | Size: 1024 | Author: 叶古 | Hits:

[VHDL-FPGA-Verilog] FIFO_ASY

Description: 异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
Platform: | Size: 2048 | Author: 253765952 | Hits:
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